Delay locked loop circuits are circuits that may be used to generate an internal clock signal that has a phase that leads a reference clock signal by a predetermined time. Internal clock signals are often used in semiconductor integrated circuits which operate in synchronization with an external clock signal and have a relatively high degree of integration such as, for example, Rambus DRAM (RDRAM) and Synchronous DRAM (SDRAM) circuits.
More specifically, in many conventional semiconductor circuits, an external clock signal is input to a clock buffer through an input pin to generate an internal clock signal. A data output buffer outputs data to an external circuit in synchronization with the internal clock signal. The internal clock signal is delayed from the external clock signal by a predetermined time in the clock buffer. The output data from the data output buffer is also delayed from the internal clock signal by a predetermined time. As a result, the output data may be output after a long delay time with respect to the external clock signal such that the output data access time (tAC) becomes long.
In order to reduce the output data access time (tAC), a delay locked loop may be used to generate the internal clock signal such that the phase of the internal clock signal leads the phase of the external clock signal by a predetermined time. Use of such an internal clock signal may allow the output data to be output without delay with respect to the external clock signal. In other words, the delay locked loop receives the external clock signal and generates an internal clock signal that has a phase that leads the external clock signal by a predetermined time. The internal clock signal may be used as a clock signal of each part of the circuit, such as the data output buffer.
FIG. 1 is a block diagram of a conventional delay locked loop circuit 100. As shown in FIG. 1, the conventional delay locked loop includes a phase detector 11, a charge pump 12, and a voltage controlled delay line 13.